1. Field of the Invention
The present invention relates to a programmable logic device suitable in the case where plural circuits are sequentially reconfigured to take on a part of processing by an application program for example. Particularly, the present invention relates to a method of reducing time required for reconfiguring a programmable logic device.
2. Description of the Related Art
In the field of a digital device, a programmable logic device such as a field programmable gate array (FPGA) and a programmable logic device (PLD) has been used for prototypical device before an application specific integrated circuit (ASIC) is produced or for a substitute device of ASIC that requires a long term for production from a few weeks to a few months. Also recently, a programmable logic device is used to change specifications after a device is produced and to enable modifying a circuit.
FIG. 22 shows the configuration of a programmable logic device in general. The programmable logic device 1 includes a circuit information input controller 2 for reading circuit information from an external device and a programmable logic circuit 3 for implementing a circuit function according to the read circuit information.
Further detailedly, the programmable logic circuit 3 includes a circuit element 4 and a configuration memory 5 connected to the circuit element 4 as shown in FIG. 23. The circuit element 4 includes an input/output device, logic circuit cells and wiring. Depending upon the configuration of the connection of the circuit element 4, the programmable logic device is classified into an FPGA type and a CPLD type.
In a programmable logic circuit 3A of the FPGA type, logic circuit cells 6A arrayed in the shape of a cross grating are mutually connected via wiring 7A as shown in FIG. 24A. Each logic circuit cell also receives a signal from a external device or outputs a signal to an external device via an input/output device 8A connected to the respective four sides of the rectangular wiring 7A when viewed as a whole.
Also, in a programmable logic circuit 3B of the CPLD type, input/output devices 8B and logic circuit cells 6B are connected to wiring 7B in tree structure as shown in FIG. 24B.
In both structure, circuit information read in the programmable logic device 1 is written to the configuration memory 5 by the circuit information input controller 2. According to the circuit information written to the configuration memory 5, the function and the connected state of the circuit element are determined. This operation is called the reconfiguration of the programmable logic device or configuration.
[Description of reconfigurable computing technique]
Recently, in the field of reconfigurable computing to implement higher speed processing than software processing using a general purpose processor by hardware processing using a dedicated processing circuit for the processing of an application, a programmable logic device is starting to be utilized.
In reconfigurable computing, the circuit information of plural processing circuits required in the processing of an application is stored in an external storage beforehand and if necessary, a required circuit is implemented in a programmable logic device by writing the circuit information read from the external storage to the configuration memory of the programmable logic device.
The technique is called cache logic technique in view of saving required circuit information outside a programmable logic device and is called virtual logic technique in view of implementing a circuit larger in scale than the scale of an actual programmable logic circuit by rewriting circuit information. In the following description, these technologies are generically called cache logic technique for simplification.
The cache logic technique is time sharing driving technique that different circuits are configured in the same programmable logic device if necessary. As a result, circuits exceeding the scale of a programmable logic device can be implemented using the programmable logic device small in scale, the device can be miniaturized and the cost can be reduced.
However, there is a problem that depending upon the scale of circuit information written to the configuration memory of a programmable logic device, it takes much time to write circuit information from an external storage to the configuration memory of the programmable logic device and the whole processing time including circuit reconfiguring time is longer than software processing time even if high speed processing is implemented using a dedicated hardware processing circuit.
One solving method of the problem is device technique called multicontext technique. That is, in the multicontext technique, plural configuration memories are provided so that plural circuit information pieces can be stored in a programmable logic device and circuit reconfiguring time is greatly reduced by reconfiguring the programmable logic device by switching the configuration memories if necessary.
[Description of programmable logic device based upon multicontext technique]
FIG. 25 shows the structure of a programmable logic device base upon multicontext technique. The programmable logic device 10 based upon the multicontext technique includes a circuit information input controller 11 that reads plural circuit information pieces from an external device, a circuit information selection controller 12 that selects required circuit information out of plural circuit information pieces and a programmable logic circuit 13 that realizes a circuit function according to the selected circuit information.
FIG. 26 shows the detailed structure of the programmable logic circuit 13 based upon the multicontext technique. The programmable logic circuit 13 includes a circuit element 14 having input/output devices, logic circuit cells and wiring as in the above case and a configuration memory 15 connected to the circuit element 14, however, the configuration memory 15 in the case of the programmable logic circuit 13 based upon the multicontext technique includes plural memory planes.
In the case of the programmable logic circuit 13 based upon the multicontext technique, in both structures of the FPGA type and the CPLD type (see FIG. 24), each of plural circuit information pieces read from an external device in the programmable logic device 10 is written to each memory plane of the configuration memory 15 by the circuit information input controller 11.
Of plural circuit information pieces written to the plural memory planes of the configuration memory 15, the function and the connected state of the circuit element 14 are determined according to circuit information on the memory plane selected according to a selection signal from the circuit information selection controller 12 and circuits are reconfigured in the programmable logic device 10.
For the format of circuit information used in a programmable logic device, there are a serial format and a parallel format and configuration operation differs depending upon these two circuit information formats. Configuration operation in the case of each circuit information format in the programmable logic device 1 shown in FIG. 22 and the programmable logic device 10 using the multicontext technique shown in FIG. 25 will be described below.
[Structure of circuit information; (I) circuit information in serial format]
FIGS. 27 show the structure of circuit information in a serial format used in a conventional type programmable logic device. As shown in FIG. 27A, circuit information includes a header HDs, a data division DTs and a footer FTs. In a programmable logic device, circuit information in the serial format is treated as serial data, however, parallel transmission and parallel memory access are enabled by delimiting in a suitable unit such as 8 bits.
The header HDs has a preamble code showing the beginning of circuit information, length count showing the data quantity of the circuit information and a delimiter code showing the end of the header HDs.
The data division DTs has plural frames. A frame means a cluster of data acquired by delimiting data stored in the configuration memory every certain quantity (normally approximately 100 to 1000 bits). The size of a frame is determined considering the facility of reconfiguring circuits in a programmable logic circuit and for example, is circuit information for one column of logic circuit cells in a longitudinal direction in the case of the FPGA type shown in FIG. 24A.
Each frame includes start field bit data STB showing the beginning of a frame, configuration data CFGD stored in the configuration memory and stop field bit data ENB showing the end of the frame as shown in FIG. 27B.
The footer FTs has a postamble code showing the end of one circuit information.
[Configuration of conventional type programmable logic device 1 based upon circuit information in serial format]
FIG. 28 is a functional block diagram for explaining configuration operation based upon circuit information in the serial format to the conventional type programmable logic device 1 shown in FIG. 22. The storage of circuit information in the configuration memory will be described below using the block diagram shown in FIG. 28.
The circuit information input controller 2 shown in FIG. 22 includes a configuration controller 2a, a length count register 2b, a selector 2c and plural shift registers 2d respectively shown in FIG. 28.
Also, the programmable logic circuit 3 shown in FIG. 22 includes the circuit element 4 and the configuration memory 5 as described above, however, in FIG. 28, in the case of the FPGA type shown in FIG. 24A for example, a programmable logic circuit is divided into sets of a configuration memory 5s for plural columns in units of one column of plural logic circuit cells for example and a circuit element 4s.
A register at each digit of each shift register 2d is connected to each memory cell of the configuration memory 5s in each column. Therefore, each shift register 2d has the number of digits for circuit information for the number of one column of logic circuit cells in the case of the FPGA type shown in FIG. 24A for example. One shift register is allocated to one column of plural logic circuit cells and shift registers 2d are provided by the number of logic circuit cells in a horizontal direction.
In the case where many logic circuit cells are provided, one shift register 2d is provided for plural columns of approximately a few to few tens of columns so that the one shift register 2d is used in common for the plural columns.
The size described above of one frame of circuit information is equivalent to data quantity of one shift register 2d.
When circuit information is read from an external storage 9 in the configuration shown in FIG. 28, the configuration controller 2a detects a preamble code in the header of the circuit information and starts configuration processing.
Length count next to the preamble code is stored in the length count register 2b. The value of the length count register 2b is decremented by one for every data shift described later of the shift register 2d and the shift register 2d is operated until the value of the length count register 2b becomes 0. Hereby, all data is sent to the shift register 2d.
The data division next to a delimiter code is sent to the selector 2c. In an initial state, the selector 2c sends configuration data to a first column of shift register 2d. The shift register 2d sequentially shifts data sent from the selector 2c. When data is shifted to the end of the shift register 2d, the selector 2c switches sending data to the next column of shift register 2d.
All data is stored in the shift register 2d by operating the shift register 2d until the value of the length counter 2b becomes 0 by repeating the operation described above.
When the shift register 2d is filled with configuration data, the data is simultaneously transferred to the whole configuration memory 5s in parallel and the programmable logic circuit 3 is reconfigured. That is, as shown in FIG. 29 for example, data is simultaneously transferred in parallel from the shift register 2d to the configuration memory 5s by connecting a latch 5L of each memory cell of the configuration memory 5s to each register of the shift register 2d and sending a latch clock LCLK to the latch 5L.
Next, when the configuration controller 2a detects a postamble code in the footer next to the data division, the configuration processing is finished.
[Configuration based upon circuit information in serial format of programmable logic device 10 based upon conventional type multicontext technique]
FIG. 31 is a functional block diagram for explaining configuration operation based upon circuit information in a serial format to the programmable logic device 10 based upon multicontext technique shown in FIG. 25. The storage of circuit information in the configuration memory in a case depending upon conventional type multicontext technique will be described below using the block diagram shown in FIG. 31.
The circuit information input controller 11 shown in FIG. 25 includes a configuration controller 11a, a length count register 11b, a selector 11c and plural shift registers 11d respectively shown in FIG. 31.
The programmable logic circuit shown in FIG. 25 is divided into sets of a configuration memory 15s for plural columns in units of one column of plural logic circuit cells for example and a circuit element 14s in the case of the FPGA type shown in FIG. 24A for example as in the example of prior art described above. In the case of this example, each column of configuration memory 15s is provided for plural memory planes as shown by a broken line in FIG. 31.
A register at each digit of each shift register 11d is connected to each memory cell of each plane of each column of configuration memory 15s. The selection of a configuration memory plane by the circuit information selection controller 12 shown in FIG. 25 corresponds to the selection of word lines W1, W2, . . . , WN shown in FIG. 30 of the memory plane of each column of configuration memory 15s.
FIG. 30 shows connection between the shift register 11d and the configuration memory 15s. Each register of the shift register 11d is connected to memory cells 15s1, 15s2, . . . , 15sN of each configuration memory plane via switches SW1, SW2, . . . , SWN. The opening/closing motion of the switches SW1, SW2, . . . , SWN can be controlled by selecting and controlling the word lines W1, W2, . . . , WN. The selection of the circuit element 14 to be configured based upon circuit information on a configuration memory plane can be controlled by opening/closing the switches SW1, SW2, . . . , SWN.
In this case, each shift register 11d also has the number of digits for circuit information for one column of logic cells in the case of the FPGA type shown in FIG. 24A for example. One shift register is allocated to one column of plural logic circuit cells and the shift registers 11d are provided by the number of logic cells in a horizontal direction.
In the case where many logic cells are provided, one shift register 11d is provided for plural columns of approximately a few to few tens of columns so that the one shift register 11d is used in common for the plural columns.
The size described above of one frame of circuit information is equivalent to data quantity in one shift register 11d for example.
In the configuration shown in FIG. 31, the circuit information of plural processing circuits required by an application program for example, that is, plural circuit information pieces stored on plural configuration memory planes are stored in the external storage 9. When first circuit information is read from the external storage 9, the configuration controller 11a detects a preamble code in the header of the circuit information and starts configuration processing.
Length count next to the preamble code is stored in the length count register 11b. The value of the length count register 11b is decremented by one for every data shift described next in the shift register and the shift register 11d is operated until the value of the length count register 11b becomes 0. Hereby, all data are sent to the shift register 11d.
Data next to a delimiter code is sent to the selector 11c. In an initial state, the selector 11c sends the data to a first column of shift register 11d. The shift register 11d that receives the data sequentially shifts the data sent from the selector 11c. When the data is shifted to the end of the shift register 11d, the selector 11c switches sending data to the next column of shift register 11d. The configuration data of first circuit information is stored in the shift register 11d by repeating the operation described above and operating the shift register 11d until the value of the length counter becomes 0.
When the shift register 11d is filled with data, the word line W1 shown in FIG. 29 is selected and first circuit information is simultaneously transferred from the shift register 11d to the memory cell 15s1 of a first configuration memory plane in parallel.
When the configuration controller 11a detects a postamble code in a footer FTs next to a data division DTs, the configuration processing of the first circuit information is finished.
Second circuit information is successively read, the shift register 11d is filled with data in the same procedure as reading the first circuit information, the word line W2 shown in FIG. 29 is selected and the second circuit information is simultaneously transferred from the shift register 11d to the memory cell 2 of the second configuration memory plane in parallel.
N pieces of circuit information is respectively stored on the respective independent memory plane of the configuration memory 15 by sequentially repeating the same procedure.
In reconfiguration, configuration data is simultaneously transferred from the memory cells of a selected memory plane in parallel by selecting a word line corresponding to selected circuit information and next sending a latch clock LCLK to the latch 15L.
[Structure of circuit information; (II) circuit information in parallel format]
FIG. 32 shows the structure of circuit information in a parallel format used in a conventional type programmable logic device. As shown in FIG. 32, circuit information includes a header HDp, a data division DTp and a footer FTp. In a programmable logic device, serial transfer, parallel transmission via buses different in capacity and parallel memory access are enabled outside the programmable logic device by delimiting circuit information in the parallel format having certain bit length, for example 32-bit circuit information in the parallel format in a suitable unit, for example every bit or every 64 bits.
The header HDp has a preamble code showing the beginning of circuit information, an option code for setting a configuration parameter such as an input clock rate of circuit information and a switch command for executing a set option and starting the reading of data.
The data division DTp has plural frames as in the case of the serial format. Each frame has a frame address FADR showing the position of the frame in a configuration memory for configuration data CFGD to be written, a data-in command DIN for instructing to write the configuration data CFGD, word count WCNT for instructing the number of words read from the configuration data CFGD and the configuration data CFGD. The footer FTp has a postamble code for instructing the end of circuit information.
Circuit information in the serial format described above is all treated as data and circuit information is passively read in the whole configuration memory by operating shift registers by the number of clocks indicated by length count. In the meantime, circuit information in the parallel format is treated as data and a command and is characterized in that configuration data CFGD is partially written to a part indicated by the frame address FADR of the configuration memory by activating the data-in command DIN.
[Configuration of conventional type programmable logic device 1 based upon circuit information in parallel format]
FIG. 33 is a functional block diagram for explaining configuration operation based upon circuit information in the parallel format to the conventional type programmable logic device 1 shown in FIG. 22. The storage of circuit information in the configuration memory will be described below using FIG. 33 and a block diagram showing a part shown in FIG. 34 of the configuration memory of the conventional type programmable logic device.
The circuit information input controller 2 shown in FIG. 22 includes a configuration controller 2e, an address generator 2f and a selector 2g respectively shown in FIG. 33. The programmable logic circuit 3 shown in FIG. 22 is divided into sets of a configuration memory 5s for plural columns having one column of plural logic circuit cells as a unit and a circuit element 4s in FIG. 33 in the case of the FPGA type shown in FIG. 24A for example.
The frame of circuit information includes configuration data for one column of plural logic circuit cells as in the case of the serial format.
As shown in FIG. 34, the bit line of each column of configuration memory 5s is connected to the selector 2g. Also, the word line of the configuration memory 5s is connected to the address generator 2f.
In the configuration shown in FIG. 33, when circuit information is read from an external storage 9, the configuration controller 2e detects a preamble code in the header HDp of the circuit information and starts configuration processing.
A parameter for configuration is set in the option code next to the preamble code. The set option is executed according to the next switch command and the reading of data is started.
First, the address FADR of the frame is read in the address generator 2f, and a bit line and a word line corresponding to the configuration memory 5s for data to be written are selected. Next, the data-in command DIN is activated, data for the number indicated by the word count WCNT is read from the configuration data CFGD and the read data is written to the configuration memory 5s via the selector 2g. This procedure is repeated for all frames.
When the configuration controller 2e detects a postamble code in the footer FTp next to the data division DTp, configuration processing is finished.
[Configuration based upon circuit information in parallel format of programmable logic device 10 based upon conventional type multicontext technique]
FIG. 36 is a functional block diagram for explaining configuration operation based upon circuit information in a parallel format to the programmable logic device 10 based upon multicontext technique shown in FIG. 25. The storage of circuit information in the configuration memory will be described below using FIG. 36 and a block diagram showing a part shown in FIG. 35 of the configuration memory of the conventional type programmable logic device based upon multicontext technique.
The circuit information input controller 11 shown in FIG. 25 includes a configuration controller 11e, an address generator 11f and a selector 11g respectively shown in FIG. 36. Also, the programmable logic circuit 13 shown in FIG. 25 includes configuration memories 15s and circuit elements 14s respectively shown in FIG. 36.
As in the case shown in FIG. 31, plural sets of the configuration memory 15s and the circuit element 14s are provided. Each configuration memory 15s is provided with plural memory planes as shown by a broken line in FIG. 36.
In this example, a frame of circuit information also includes configuration data for one column of a memory cell array for one plane as in the case of the serial format.
As shown in FIG. 35, bit lines of each configuration memory 15s (including plural memory planes (a memory cell array)) are connected to the selector 11g. In this case, the bit lines of the memory cell array including plural memory planes are united and connected to the selector 11g. Also, a word line united every memory cell array including plural memory planes of the configuration memory 15s is connected to the address generator 11f.
The circuit information selection controller 12 shown in FIG. 25 corresponds to selecting the configuration memory 15s depending upon context shown in FIG. 35.
In the configuration shown in FIG. 36, when first circuit information is read from the external storage 9, the configuration controller 11e detects a preamble code in the header HDp of the circuit information and starts configuration processing.
A parameter of configuration is set by an option code next to the preamble code. Next, the set option is executed according to a switch command and the reading of data is started.
The address FADR of a frame is read in the address generator 11f, and a bit line and a word line respectively corresponding to the configuration memory 15s for data to be written are selected. At this time, as shown in FIG. 35, as plural memory cell arrays are arranged in a row, a bit line of a first memory cell array 15s1 is selected for first circuit information by the selector 11g for example.
Next, a data-in command DIN is activated, data for the number indicated by word count WCNT is read from configuration data CFGD and is written to the configuration memory 15s via the selector 11g. This procedure is repeated for all frames.
When the configuration controller 11s detects a postamble code in the footer FTp next to a data division DTp, the configuration processing of the first circuit information is finished.
Second circuit information is successively read and is stored in a second memory cell array 15s2 selected by the selector 11g according to the same procedure as that in the reading of the first circuit information. The same procedure is sequentially repeated and N pieces of circuit information is stored in the configuration memory 15.
In reconfiguration, a context selecting line corresponding to selected circuit information is selected and the configuration of the circuit element 14s is executed.
[Processing operation by circuit reconfigured based upon conventional type multicontext technique]
Next, referring to an explanatory drawing shown in FIG. 37 and a flowchart shown in FIG. 38, a procedure for operation for reconfiguring a programmable logic device based upon circuit information in case one processing using plural circuits is executed using the programmable logic device based upon conventional type multicontext technique described above will be further described.
As described above, circuit information normally has a unit called a frame, however, an example shown in FIG. 37 shows that one circuit information is configured by five frames and one processing is executed using three circuit information pieces of circuit information 1, circuit information 2 and circuit information 3.
That is, the three circuit information pieces (the circuit information 1, the circuit information 2 and the circuit information 3) are stored in the configuration memory 15 via the circuit information input controller 11. One circuit information is selected out of the three circuit information pieces stored in the configuration memory 15 according to a selection signal generated by an application program for example by the circuit information selection controller 12 and the programmable logic device 10 is reconfigured based upon the circuit information.
Referring to the flowchart shown in FIG. 38 and a timing chart shown in FIG. 39, this procedure for reconfiguration will be described below. In the timing chart shown in FIG. 39, the programmable logic device is reconfigured using the circuit information 1, the circuit information 2 and the circuit information 3 in the order and processing is finished.
First, the circuit information input controller 11 reads circuit information stored in an external storage (not shown) and others one by one and stores it in the configuration memory 15 (a step S101). At this time, every time the circuit information input controller reads circuit information, it checks the residual capacity of the configuration memory 15 (steps S102 and S103) and when the configuration memory 15 is full before all circuit information pieces are read, the circuit information input controller detects an error and terminates the operation (a step S104).
When the circuit information input controller 11 stores all the three circuit information pieces in the configuration memory 15, the circuit information selection controller 12 monitors a selection signal (a step S105). When the circuit information selection controller 12 detects that a selection signal is switched according to an application program for example, the circuit information selection controller identifies which of the three circuit information pieces is selected (a step S106), circuit information according to the switched selection signal is read from the configuration memory 15 and the programmable logic circuit (not shown) is reconfigured according to the circuit information (a step S107 or a step S108 or a step S109).
Afterward, as long as processing by the programmable logic device 10 continues, the monitoring of a selection signal by the circuit information selection controller 12 is continued and every time a selection is switched, circuit information is switched. When processing by the programmable logic device 10 is finished, the procedure for reconfiguration is finished independent of a selection signal.
In the case where processing by the programmable logic device 10 is finished, the programmable logic device is generally kept in a state reconfigured based upon finally selected circuit information unless power supply to the programmable logic device 10 is stopped.
Referring to the timing chart shown in FIG. 39, the processing described above will be further described below. That is, when processing becomes an execution state, the three circuit information pieces 1, 2 and 3 are first read in the configuration memory 15. When the reading is finished and the selection of circuit information is instructed, a configuration memory plane where the circuit information the selection of which is instructed is stored is selected to be switched, the circuit information is read and the programmable logic circuit is reconfigured based upon the read circuit information.
The reason why configuration based upon the circuit information 3 is also continued after execution is finished in FIG. 39 is that a programmable logic device is generally kept in a state reconfigured based upon finally selected circuit information unless power supply is stopped in case processing is finished as described above.
[Concrete conventional examples using multicontext technique]
For one of multicontext techniques described above, there is "a multifunctional programmable logic device" disclosed in Japanese Published Unexamined Patent Application No. Hei 2-130023. Referring to FIG. 40, this example will be described below as a conventional example 1.
FIG. 40 shows the configuration of a multifunctional programmable logic device. This device includes a programmable logic array 21, PROM 22 for setting a switch having SRAM and a selecting circuit 23.
PROM 22 for setting a switch can store M sets of N-bit circuit information corresponding to a circuit having the programmable logic array 21. The circuit configuration of the programmable logic array 21 is determined by one set of circuit information selected by the selecting circuit 23 out of M sets of circuit information stored in PROM 22 for setting a switch. That is, the circuit configuration of the programmable logic array 21 can be reconfigured by switching circuit information selected by the selecting circuit 23.
For another example based upon multicontext technique, there is "Time-Multiplexed FPGA" announced in FPGAs for Custom Computing Machines 1997 (FCCM'97). Referring to FIG. 41, this will be described below as a conventional example 2.
FIG. 41 shows the configuration of the announced time sharing driven FPGA. The time sharing driven FPGA is acquired by improving XC4000E manufactured by Xilinx (U.S.A.) and is provided with 8 sets of configuration memories 25 having SRAM that determine the logic cells of a circuit element 24 and internal wiring. Circuit information corresponding to different circuit configuration is stored in the respective configuration memories 25 and FPGA can be reconfigured by time sharing by switching these configuration memories 25.
As shown in the conventional examples 1 and 2, multicontext technique enables reducing time required for reconfiguring a circuit because plural circuit information pieces are stored in the configuration memory beforehand.
However, as plural planes or plural configuration memories are required inside a programmable logic device to store circuit information, the scale of the programmable logic circuit is increased. When the scale is increased, a problem that the performance of the circuit is deteriorated because the load capacity of the circuit element is increased and power consumption is increased is caused. Also, when the scale of the circuit is increased, a problem that the manufacturing cost of the programmable logic device is increased is caused.
Normally, as a programmable logic device is manufactured in CMOS process, SRAM that can be manufactured in the same CMOS process is used for a configuration memory. In the conventional examples 1 and 2, SRAM is used for a configuration memory. As SRAM requires six transistors to store one bit, the scale of a programmable logic circuit is greatly increased when the number of circuit information pieces that can be stored in the programmable logic device is increased.
The problem that the scale of a circuit is increased as described above is improved to some extent by using DRAM having three transistors per bit for a configuration memory as "First Generation DPGA Implementation" announced in Third Canadian Workshop of Field Programmable Devices 1995 (FPD'95). Referring to FIG. 42, this will be described below as a conventional example 3.
FIG. 42 shows the logic cell structure of announced DPGA. A logic cell includes 4.times.32-bit DRAM 31 that can store four sets of configuration, four eight-input multiplexers 32 to 35, a four-input look-up table 36, a bistable circuit 37 and a selector 38 for switching output.
Out of the output of 32-bit DRAM 31, 12 bits determine the state of the four eight-input multiplexers 32 to 35, 16 bits determine the state of the four-input look-up table 36, one bit determines the state of the selector 38 and the residual 3 bits are reserved. Circuit information pieces respectively different are stored in four sets of DRAM 31 and a different circuit can be configured by switching the output of the memory.
As described above, as DRAM 31 is configured by three transistors per bit, the problem that the scale of the circuit is increased in multicontext technique can be improved to some extent according to the conventional example 3.
Further, a CMOS circuit and DRAM having one transistor per bit can be manufactured on one device owing to the recent development of semiconductor device manufacturing technology. The semiconductor manufacturing technology is called a DRAM consolidation process. To store in one bit, SRAM having CMOS requires six transistors and DRAM having CMOS requires three transistors, while DRAM according to the DRAM consolidation process requires only one transistor.
Therefore, the above defect that an extra configuration memory area is required to store circuit information of multicontext technique can be further improved by using DRAM having one transistor according to the DRAM consolidation process for a configuration memory.
For the example, there is "an Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration" announced in Symposium on VLSI Circuit 1997. Referring to FIG. 43, this will be described below as a conventional example 4.
FIG. 43 shows the structure of the announced DRAM-FPGA logic elements and a DRAM element, and four logic elements 42 to 45 surround the DRAM element 41 having 256.times.256 cells. One logic element is reconfigured based upon 64-bit circuit information. Each 64-bit bit line led out by total 128 bits right and left via a sense amplifier is connected to each logic element 42 to 45.
Circuit information output to the right and left bit lines is switched by selecting a word line led out by 128 bits upward and downward via a word driver. That is, DRAM-FPGA can store 256 sets of circuit information by using the DRAM element 41 for a memory circuit.
As shown in the conventional example 4, the defect that an extra configuration memory circuit area is required to store circuit information of multicontext technique can be greatly improved by constituting a memory circuit by DRAM having one transistor using the DRAM consolidation process.
However, as a gate oxide film of a transistor used in the DRAM circuit is required to be thicker than a gate oxide film of a transistor used in the CMOS circuit, they are required to be separately produced. Therefore, a new problem that the number of processes is increased, the manufacturing cost of the programmable logic device is increased and a yield is deteriorated is caused. Also, when processes are shared and a thick oxide film is used not to increase the number of processes, another problem that the performance of the CMOS circuit is deteriorated is caused.
As described above, an information processing system using reconfigurable computing technique that a part of processing by an application program is processed by a circuit having the programmable logic device using cache logic technique has a problem that time required for reconfiguring a circuit is increased and hardware processing by a programmable logic device originally faster in processing speed, compared with software processing may require more time than software processing when both processing is compared in total processing time including circuit reconfiguring time.
Multicontext technique which is one unit for solving the problem can reduce time required for reconfiguring a circuit, however, as an extra configuration memory area to store plural circuit information pieces is required, the multicontext technique has a defect that the scale of a programmable logic circuit is increased.
When the scale of the circuit is increased, a problem that the load capacity of a circuit element is increased, the performance of the circuit is deteriorated and power consumption is increased is caused. Also, when the scale of the circuit is increased, a problem that the manufacturing cost of the programmable logic device is increased is caused.
Also, to reduce a configuration memory area, DRAM having one transistor manufactured according to the DRAM consolidation process is used for a memory in place of SRAM manufactured according to a CMOS process. However, as described above, a new problem that the number of processes is increased, the manufacturing cost of the programmable logic device is increased and a yield is deteriorated is caused. Also, when processes are shared not to increase the number of processes and a thick oxide film of DRAM is used for an oxide film of a CMOS circuit, another problem that the performance of the CMOS circuit is deteriorated is caused.